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Related Topics: CEOs in Technology, Intel Virtualization Journal, Datacenter Automation


Intel Wants To Re-Architect the Data Center

Intel last week reported Q2 revenues down 5% year-over-year to $12.8B while returning earnings of $2B in line with expectations

Intel wants to re-architect the data center to rapidly deliver new services efficiently and at scale through the cloud in an age of massively growing network connections and scads of real-time unstructured data, not to mention its need to ensure its own continued relevance and growth.

With no real mobile business to offset the global plunge in PC sales, down lately 11% year-over-year, Intel last week reported Q2 revenues down 5% year-over-year to $12.8 billion while returning earnings of $2 billion in line with expectations. It trimmed its Q3 expectations to $13.5 billion plus or minus $500 million.

Then on Monday it trotted out some of its near-term and longer-term plans lest ARM, the mobile chip leader, and its entourage leach away some of its influence.

These spotty plans include Intel’s imminent next-generation 22nm Atom processors Avoton and Rangeley, now grouped together officially as the C2000 family, as well as a 14nm Atom chip code-named Denverton, due out next year.

Intel             low-power server roadmap

Avoton, which come to find out has been sampling since April, is aimed at low-energy, high-density microservers and storage, Rangley at network devices.

The widgets, which will support a maximum 64GB of DDR memory and Intel’s virtualization technology, are based on the company’s Silvermont microarchitecture and will be tricked out with up to eight cores, integrated gigabit Ethernet, 16 PCI Express lanes and SATA controller circuitry.

These second-generation 64-bit Atom widgets are supposed to deliver four times the energy efficiency and up to seven times the performance of their first-generation 32nm SoC predecessors released in December.

Intel claims Avoton’s got double the design-wins of the months-old Centerton or S1200 Atoms used in HP’s Moonshot project (50, in fact, it said) and claimed it will beat ARM on power efficiency on a per-core basis.

Intel has also added a new Xeon SoC to its roadmap that’s designed for the data center with built-in connectivity and memory using its next-generation Broadwell chip, the follow-on to its Haswell Xeon microarchitecture.

The dingus is supposed to be the first SoC based on a high-performance architecture and is meant to offer still higher performance in highly dense, energy-efficient systems although Intel didn’t say how dense, how efficient or how performant. It did say the part will have an on-board fabric interconnect, I/O and accelerators.

There’s also an apparently true Xeon Broadwell, set for release next year, that’s not a SoC but should dissipate less power than its forebears. How much less is unclear.

Last week Intel’s new CEO Brian Krzanich (pictured) said that he means to make Atom chips as important, and presumably as revenue-producing, as the Core chips used in PCs, and that means pushing the pedal on the process technology used to churn them out. Intel’s Xeon, Core and Atom chips and its process technology should synch up next year.

Intel is suddenly showing a new willingness to modify its CPUs and SoCs for server customers using hardware and software accelerators that tickle the performance of specific workloads and the devices that connect to them. Evidently it developed custom chips for eBay and Facebook and now it’s developing an accelerator to improve Nuance Communications’ voice recognition.

It’s got a so-called Rack Scale Architecture (RSA), described as an advanced design that it says promises to dramatically increase server utilization – currently 50% or less of capacity – as well as the flexibility of the data center to deliver new services.

In the first commercial rack-scale implementation Rackspace is deploying new Xeon- and Atom-based server racks and Intel Ethernet controllers with storage accelerated by Intel Solid State Drives.

Intel claims flash is key to turning static storage dynamic so it can crunch through the amount of data that storage is currently being asked to deal with. It estimates SSD can sort through 1TB of data in seven minutes where HDD-based storage takes four hours.

It’s also talking about software-defined infrastructure like applications that ask for the resources they need and virtualized networking that, it says, can cut the time needed to provision a new service from two or three weeks to a few minutes – a comparison Intel derived internally – and so it’s introduced Open Network Platform reference designs to help OEMs build and deploy this new generation of networks.

By equipping the network with open, general-purpose processing capabilities, as it has apparently done with RSA, the widgetry is supposed to maximize network bandwidth and significantly reduce cost.

Intel means to add computational functionality to the five million base stations operated globally by telecoms to its idea of a software-defined network to reduce latency and slash the time it takes to deliver content and services to users on the edge of the cellular network.

Intel imagines a “virtuous cycle of computing” consisting of machine-to-machine (M2M) devices connected to the data center, services and end users and still more devices dependent on a more scalable and efficient back-end.

Disney, for instance, has reportedly spent close a billion dollars to provide visitors to Disney World with wirelessly connected wristbands to enhance their in-park experience through real-time data analytics.

Intel's Raejeanne Skillern speaking at 11th Cloud Expo / Cloud Expo Silicon Valley (2012)

Intel’s also imagining servers, predicated on power-sipping Atom chips, that deliver pooled compute, pooled memory, pooled I/O, pooled storage and pooled networking for application-driven resource allocation, reduced redundancy and lower power consumption in a tighter space.

More Stories By Maureen O'Gara

Maureen O'Gara the most read technology reporter for the past 20 years, is the Cloud Computing and Virtualization News Desk editor of SYS-CON Media. She is the publisher of famous "Billygrams" and the editor-in-chief of "Client/Server News" for more than a decade. One of the most respected technology reporters in the business, Maureen can be reached by email at maureen(at)sys-con.com or paperboy(at)g2news.com, and by phone at 516 759-7025. Twitter: @MaureenOGara

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