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Intel Plans Giant Co-Processor

It means to create supercomputers that run most of their workloads on Xeon chips

Intel has started laying the groundwork for what it says will eventually be at least a 50-core x86 co-processor called Knights Corner based on a newfangled Many Integrated Core (MIC) architecture.

It says the widget, the first of a family of Knights, will create HPC platforms running at trillions of calculations a second without sacrificing the benefits of standard x86 processors, a hard-won lesson learned from its Itanium adventure.

It means to create supercomputers that run most of their workloads on Xeon chips but accelerate specific highly parallel applications complements of the MIC architecture.

The anticipated 500 gigaflops systems will be aimed at uses such as exploration, scientific research and financial simulation.

According to none other than DreamWorks Animation CEO Jeffrey Katzenberg speaking at the chatty D8 conference the other day, Intel also has workstation intentions for the thing, and the reason he called the thing Larrabee despite the fact that Intel canceled the prospective GPU last week is because the thing is Larrabee redirected.

In the initial 32nm developer prototype version that's floating around out there Knights is a 32-core Larrabee. The first commercial product will be a 22nm 50-core device that derives not only from the canceled Larrabee but also from the research-y ultra-low-power 48-core Single-Chip Cloud Computer that Intel disclosed in December and TeraScale.

Larrabee, as Intel puts it, will "use Moore's Law to scale to more than 50 processing cores on a single chip." Each of the cores will reportedly run at 1.2GHz, have 8MB of shared coherent cache and four threads apiece for a total of 128 threads. It'll also support 1GB-2GB of GDDR5 memory.

The company's already got design and development kits codenamed Knights Ferry shipping to hand-picked developers, and beginning in the second half it means to start delivering MIC developer tools. The trick is that they will share a lot of in common with Xeon tools as well as common software algorithms and programming techniques. The same languages, compilers and libraries can be used. It eliminates the need for a dual-programming architecture.

Apparently the CERN openlab team was able to migrate a complex C++ parallel benchmark to the MIC software development platform in just a few days. Its CTO Sverre Jarp said that "the familiar hardware programming model allowed us to get the software running much faster than expected."

Since the dingus is 22nm it can't go commercial until next year.

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Maureen O'Gara the most read technology reporter for the past 20 years, is the Cloud Computing and Virtualization News Desk editor of SYS-CON Media. She is the publisher of famous "Billygrams" and the editor-in-chief of "Client/Server News" for more than a decade. One of the most respected technology reporters in the business, Maureen can be reached by email at maureen(at)sys-con.com or paperboy(at)g2news.com, and by phone at 516 759-7025. Twitter: @MaureenOGara

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